1. Field of the Invention
The present invention relates to a current source cell apparatus for a digital/analog converter, and in particular to an improved current source cell apparatus for a digital/analog converter which is capable of reducing noise which occurs due to switching of the current source cell, for thus obtaining a faster setting and being well suited to a high frequency digital/analog converter.
2. Description of the Conventional Art
FIG. 1 is a circuit diagram illustrating a conventional current source cell for a digital/analog converter, which was disclosed in Miki, T. et al., "An 80-Mhz 8-bit CMOS D/A converter", IEEE Journal of solid-state Circuits, Vol. SC-21, No. 6, December 1986, PP. 370-375.
As shown in the above-mentioned article, a conventional current source cell for a digital/analog converter includes a row decoder and column decoder for decoding an input digital signal, and a plurality of current source cells are arranged in a matrix and selected by the row decoder and column decoder for generating a source current.
In each conventional current source cell, there are provided a first NMOS transistor Q1 having its gate connected to receive a first bias voltage VG1, and its source connected to a ground potential Vss. A second NMOS transistor Q2 has its source connected with the drain of the first NMOS transistor Q1, its gate connected to receive a second bias voltage D, and its drain connected to a supply voltage Vcc. A third NMOS transistor Q3 has its source connected with the drain of the first NMOS transistor Q1, its gate connected to receive an inverted complementary voltage DB of the second bias voltage terminal Vout. A load resistor R1 receiving the supply voltage Vcc is also connected with the output voltage terminal Vout. A capacitor shown connected between the gate and drain of transistor Q3 in FIG. 1 represents a stray capacitance between DB and Vout.
The conventional current source cells in the matrix array are all commonly connected to the output voltage terminal Vout.
The operation of the conventional current source cell will now be explained with reference to FIG. 1.
The NMOS transistor Q1 is a current source transistor and controls the level of a full scale current in accordance with the first bias voltage Vg1. The NMOS transistors Q2 and Q3 are current switches and are operated in saturation.
When the NMOS transistor Q2 is turned on in accordance with the second bias voltage D, the NMOS transistor Q3 is turned off in accordance with the inverter voltage DB complement of the second bias voltage D, so that current is not applied to the output voltage terminal Vout.
On the contrary, when the NMOS transistor Q2 is turned off in accordance with the second bias voltage D, the NMOS transistor Q3 is turned on by the inverted voltage DB complement of the second bias voltage D, so that a predetermined level of current flows to the ground voltage Vss, the output voltage Vout is determined by the resistor R1. Therefore, the level of the output analog signal is determined.
Namely, when the NMOS transistor Q1 is turned on and the NMOS transistor Q3 is turned on, the supply voltage Vcc is applied across the load resistor R1, and the level of the output voltage is determined in accordance with the voltage drop due to the load resistor R1.
However, when the conventional current source cell is switched, digital switching noise affects the current source, so that a predetermined time lapse is needed until the output voltage has a stable level. Such predetermined time lapse is called the "Setting time", when is an important factor which determines the performance of the digital/analog converter.
FIG. 2 is a circuit diagram illustrating another conventional current source cell for a digital/analog converter, as was disclosed in U.S. Pat. No. 4,904,922.
As shown therein, this conventional current source cell for a digital/analog converter includes a first PMOS transistor Q10 the gate of which receives a first bias voltage Vg1, the source of which receives the supply voltage Vcc, and the drain of which is connected with a common node Vx, a second PMOS transistor Q20 the gate of which receives a second bias voltage D, the source of which is connected with the drain of the first PMOS transistor Q10 through the common node Vx, and the drain of which is connected with a ground voltage Vss, a third PMOS transistor Q30 the source of which is connected with the drain of the first PMOS transistor Q10 through the common node Vx, the gate of which receives a reference voltage RVg, and the drain of which is connected to an output voltage terminal Vout, and a load resistor R1 connected between the drain of the third PMOS transistor Q30 and the ground voltage Vss.
The PMOS transistor Q10 is a current source transistor and determines the level of the current, and the PMOS transistor Q20 is a switching transistor and switches the current being applied to the output voltage terminal Vout.
Namely, when the PMOS transistor Q20 is turned off, a current determined by the PMOS transistor Q10 is applied to the output voltage terminal Vout through the PMOS transistor Q30 which determines the analog output. In addition, when the PMOS transistor Q20 is turned on, the electric potential of the common node Vx becomes the ground voltage Vss, and no current is applied to the output voltage terminal Vout.
Here, the PMOS transistor Q30 is operated in the saturated region by the reference voltage RVg.
As described above, this second conventional current source cell apparatus is directed to preventing the noise generated due to the second bias voltage D from being transferred to the current source by using the PMOS transistor Q30 which is controlled by the reference voltage RVg; however, it degards to obtain a faster switching operation becase of the delay time of another transistor Q30 is impossible to obtain a faster switching operation, thus causing a slow digital/analog conversion.